always @(posedge DCFclk) begin           // DCFclock is 100MHz
  if(clk120strobe) begin                 // once every chip, rate= 77500/120 Hz
    CORRresult<=CORRsum ;                // save last result
    CORRcntr<=0 ;                        // restart correlation
    LFSR<=1  ;                           // restart LFSR
    CORRsum<=0 ;                         // init correlation sum
    buffer[WritePtr]<=phase32 ;          // put new sample into buffer
    WritePtr<=WritePtr+1'd1 ;            // and advance position
    ReadPtr<=WritePtr ;                  // correlation starts there
    end
   else if (CORRcntr<512) begin          // we have 512 chips
    CORRcntr<=CORRcntr+1'd1 ;            // count here
    if (LFSRfeedback) begin              // LFSR==1 means +1 LFSR==0 means -1
      CORRsum<=CORRsum+buffer[ReadPtr] ; // correlation sum
      end 
     else begin
      CORRsum<=CORRsum-buffer[ReadPtr] ; 
      end 
    ReadPtr<=ReadPtr+1'd1 ;              // address next chip in buffer
    LFSR<= (LFSR << 1) | LFSRfeedback ;  // compute next LFSR chip
    end 
  end
